1) WMA L1: Only 44.1 KHz is supported upto 160 kbps.
2) WMA L2: Includes WMA L1, plus upto 48 KHz sampling rate at 256 kbps.
3) WMA L3: Full implementation. Includes WMA L1 and WMA L2 plus bitrates of 192-320 kbps for both 44.1 and 48 KHz sampling rates.
4) WMA L: PC only profile intended to showcase full codec capabilities and is not intended for devices.
5) WMA Pro M0: Sampling frquency less than 48 Khz, support upto 192 kbps and mono and stereo channels.
6) WMA Pro M1: Sampling frquency less than 48 Khz, support upto 384 kbps and multi channel support up to 5.1.
7) WMA Pro M2: Sampling frequency less than 96 Khz, support upto 768 kbps and multi channel support up to 5.1.
8) WMA Pro M3: Sampling frequency less than 96 Khz, support upto 1.5 Mbps and multi channel support up to 7.1.
9) WMA Pro M: PC profile supports all the sampling frequency, bit rate and channels, intended to showcase full codec capabilities.
- WMA Standard
- Supports WMA 7,8, 9, 9.1 and 10
- Profiles – L1 to L3
- Sampling frequency : 8 – 48 Khz
- Channels: stereo
- All bitrates of WMA L3 profile
- WMA Pro
- Sampling frequency : 8 – 96 Khz
- Channels – Upto 7.1
- Profile – M0 to M3
- PCM resolution – 16 and 24 bits
- Low Mhz and memory foot print
- Re-sync support for fast forward/rewind
- Multi instance and re-entrant implementation
- XDM API support for TI processors
- API supports push model type
- Automotive Infotainment
- Portable audio players
- Mobile phones
- Gaming consoles
- Broadcast audio
- TMS320C67x, TMS320C66x
- ARM9, ARM11,Cortex A8
Developing an Asynchronous Sample Rate Converter
Designing an Asynchronous Sample Rate converter that offers high THD and low ripple across a range of frequencies is no mean achievement. We not only designed the ASRC but implemented it with low MHz on a fixed point processor.
Video codecs on a multi-core highly-parallel custom core
We worked with SiliconHive (now part of Intel) to develop High Definition video codecs that are designed to run optimally on a multi-core environment. Our contribution also included efficient coding for a VLIW core and algorithmic innovations to address memory bandwidth constraints.